Fiege, Nicolai

This is the code used to produce results for the publication "Multiplexer Optimizations for Virtex FPGAs" by N. Fiege, M. Hardieck and P. Zipf, presented at the 35th International Conference on Field-Programmable Logic and Applications (FPL) in Leiden, Netherlands during September, 2025.
The README.md file contains the VHDL code describing the multiplexers as well as all necessary information to reproduce the results presented in the paper. We are actively working on applying these optimizations to other FPGA architectures within the following repository: https://gitlab.uni-kassel.de/uk025743/mux_opt

Abstract:
Multiplexers (MUX) are essential elements in Field-Programmable Gate Arrays (FPGA), widely used in practical applications. Due to the LUT-based architecture of FPGAs, multiplexers that switch among many signals or operate on large word sizes incur significant resource costs, as these costs scale linearly with the data word size. Vivado’s automatic synthesis flow often produces sub-optimal MUX implementations, necessitating hand-crafted solutions to minimize resource overhead. Here, we present three MUX implementation schemes that reduce resource usage for various input signal counts. These optimizations enable enhanced resource efficiency in applications ranging from circuits generated by High-Level Synthesis (HLS) tools to optimized digital filters and artificial neural networks.